Before Computex: Huang Meets TSMC, AMD Announces $10 Billion Investment in Taiwan
Nvidia's Huang meets with TSMC, AMD's Su invests $10 billion in Taiwanese packaging, crucial for GPU supply and DACH cloud architects ahead of Computex.
6 min read
Nvidia CEO Jensen Huang touched down in Taipei on Saturday, 24 May-eight days before his GTC keynote on 1 June and in parallel with a stop at TSMC, where the Vera Rubin ramp is hanging in the balance. Four days earlier, on 20 May, AMD CEO Lisa Su arrived in the same city with a press release in tow: more than 10 billion US dollars invested in Taiwan’s advanced packaging ecosystem over three years, with ASE and SPIL as the central partners. For DACH cloud architects, this isn’t an Asia-Pacific story-it’s an H2 signal.
26 May 2026
Key Takeaways
- Dual appearances ahead of Computex: Su since 20 May in Taipei with a $10 billion announcement, Huang since 24 May with a TSMC stopover. Both CEOs land a week before the largest-ever Computex (1,500 exhibitors, four venues, 2–5 June).
- AMD’s move targets advanced packaging: Partners ASE and SPIL, technology Elevated-Fan-Out-Bridge (EFB). This directly addresses the CoWoS bottleneck that currently constrains Nvidia’s supply chain.
- Implications for cloud teams: Vera Rubin volumes remain tight, inference slots grow costlier, and AMD’s Instinct line becomes a serious secondary option in H2 procurement. Anyone planning 2026 solely around Nvidia should broaden their sourcing model now.
Related:AWS and Nvidia: GPU million forces platform teams to rethink / FinOps for AI inference
What really happened in Taipei over the weekend
What is advanced packaging? Advanced packaging refers to the stack-and-bond process between logic die and high-bandwidth memory that turns a modern AI GPU into a usable product. TSMC’s CoWoS is the best-known variant; AMD’s Elevated-Fan-Out-Bridge is its answer. Whoever controls this capacity dictates the rollout pace of the next GPU generation.
The sequence of events reveals the playing field. Su staked AMD’s claim in the window when every eye was already on Taipei. Huang arrived later, but with the bigger gesture: a pilgrimage to TSMC and a public vow that Vera Rubin is the largest product launch in the island’s history.
Computex Week Timeline
- Wed 20 May: AMD CEO Lisa Su arrives in Taipei. AMD IR press release announces more than $10 billion in ecosystem investments over three years, focused on advanced packaging with ASE and SPIL.
- Thu 21 May: Reuters and CNBC verify the investment scale. Su visits TSMC to secure 2 nm capacity.
- Sat 24 May: Nvidia CEO Jensen Huang lands in Taipei in the afternoon. First statement: Vera Rubin is the largest product launch in Taiwan’s history.
- Sun–Mon 25–26 May: Huang meets TSMC to align ramp schedules. Side meeting with local developer community.
- Mon 1 Jun: GTC Taipei keynote at Taipei Music Center, 11 a.m. local time. Computex opens 2 Jun across four venues in Taipei.
The primary source for AMD’s move is the 20 May investor-relations release. It names EFB technology and explicitly pegs the volume over three years. Reading this as mere marketing underestimates the point: AMD is placing capital exactly where Nvidia’s bottleneck sits today.
Why packaging capacity is reshaping the playing field
CoWoS was the single largest bottleneck in the AI stack in 2024 and 2025. Nvidia’s H100 and H200, followed by Blackwell, were all constrained by TSMC’s CoWoS capacity because high-bandwidth memory cannot be cleanly attached to the GPU without advanced packaging. Anyone who placed an order for a GB200 eighteen months ago is still waiting for delivery.
AMD’s 10-billion-dollar bet isn’t on the wafer itself; it’s on this packaging layer. ASE and SPIL are Asia’s two largest OSATs, and the Elevated-Fan-Out Bridge (EFB) is AMD’s in-house answer to CoWoS-L. A three-year timeline sounds like a master plan, not a knee-jerk reaction.
At the same time, Huang made the message behind his opening salvo crystal clear: Vera Rubin is the biggest product launch in the history of the island. That’s marketing speak, but it has a hard edge-Nvidia is locking the next GPU generation even tighter to TSMC’s roadmap. AWS publicly revealed its million-GPU order four days ago, and Microsoft, Meta and Google have penciled in similar volumes for 2026. If packaging capacity stays tight, the bulk of supply will flow to hyperscalers, leaving less for mid-market clusters in the DACH region.
Three takeaways for DACH cloud architects
Computex week is not an Asian headline for European platform teams-it’s an early indicator for the second half of the year.
First: inference slots remain scarce. If you’re planning GPU inference capacity for H2, don’t bet on falling spot prices. Hyperscalers are absorbing volume, shrinking the secondary market for inference. The FinOps lessons of the past few months still hold: reservations make sense, on-demand becomes an expensive last resort.
Second: AMD Instinct is now a must-have in the sourcing mix. Until mid-2025, AMD’s MI300 was often a nice-to-have alternative for DACH cloud teams. With the packaging bet and the upcoming MI355X availability, that calculus changes. If your 2026 plan is exclusively Nvidia, it’s time to revisit the procurement model-not out of brand loyalty, but because supply security has become the second axis of decision-making.
Third: inference architecture matters more than the next GPU generation. If scarcity persists, the lever isn’t the next vendor briefing; it’s your own inference layout. Quantization, KV-cache strategy, batch routing across cloud regions-these levers have a bigger impact on the bill than swapping an H200 for an H100. The inference playbook is a more practical starting point than another hyperscaler contract.
What remains open until Monday’s keynote
Three questions are still unanswered ahead of the GTC-Taipei keynote on 1 June. First, whether Huang will give a concrete Vera Rubin availability timeline for DACH hyperscaler regions. Second, whether TSMC will publicly respond to AMD’s packaging bet-perhaps with its own CoWoS expansion figure. Third, whether a German OEM will take the stage at Computex and announce a mixed-configuration switch to Nvidia plus AMD.
Until then, the pragmatic move for cloud architects is clear: scrutinize the sourcing model, treat the inference stack as the primary cost lever, and stop treating GPU strategy as a brand choice.
Frequently Asked Questions
What does Su and Huang’s dual Computex appearance mean for GPU supply in the DACH region?
Nothing in the short term. A lot in the medium term. Over the course of 2026, hyperscalers will lock up the bulk of packaging capacity at TSMC and, increasingly, at ASE and SPIL. DACH cloud teams planning to run their own GPU servers should factor in longer lead times for GB200 and MI355X and treat mixed-lineup builds as Plan A, not Plan B.
Is AMD Instinct already a viable inference platform today?
For many inference workloads, yes. MI300 and MI355X deliver competitive tokens-per-second and dollars in memory-bandwidth-bound scenarios. The software gap versus CUDA is closing: ROCm 7 now covers most LLM stacks. Teams already using quantization, vLLM or TGI can realistically test AMD today.
What’s the difference between CoWoS and Elevated-Fan-Out-Bridge?
CoWoS places the dies on a silicon interposer; EFB uses bridge structures to connect the logic die and HBM stacks. For architects, EFB scales differently in area and eases TSMC’s classic CoWoS bottlenecks. If AMD’s approach lives up to its investment promise, a second, independent packaging source could emerge in 2027.
How should cloud architects adjust their H2 procurement plans now?
First, stop reserving GPUs only from Nvidia-include AMD SKUs in the sourcing model. Second, audit inference workloads to see which are bandwidth-bound rather than compute-bound, where AMD’s advantage lies. Third, lock in reservation windows with hyperscalers for Q3 and Q4 before the Computex announcements inflate demand further.
Which Computex keynote should a cloud architect watch live on 1 June?
Jensen Huang’s GTC-Taipei keynote at 11 a.m. Taipei time. Two things matter: will a concrete Vera-Rubin delivery date be named for hyperscaler regions outside the U.S.? And will there be any statement on the software layer-how CUDA and NIM position against ROCm and Triton? Both directly influence Q3 architecture decisions.
Image source: Pexels / panumas nikhomkhai (px:37730212)
